The present invention relates to a semiconductor device including contacts self-aligned with the gate electrode thereof, and also relates to a method for fabricating such a device.
Recently, semiconductor devices of older generations have been replaced with newer ones in at shorter and shorter cycles and the number of miniaturized devices integrated together on a single chip has been steeply rising. Reflecting these tendencies, the size of a contact hole, which is used to interconnect together the gate electrode, diffused layer and interconnection layer of an MOS transistor, has been decreasing. That is to say, the size of a contact, which is formed by filling in the contact hole with a conductive material, has been decreasing year after year. As the design rule has been minimized at such an increasing rate, it has become more and more difficult for the mask overlay accuracy to catch up with such rapid downsizing. Thus, the resultant increase in number of devices integrated is not so striking as the size reduction accomplished.
To ensure much more margin in stacking masks, a technique of forming a contact to be self-aligned with a gate electrode has been vigorously researched and developed these days. In this specification, such a contact will be simply referred to as a xe2x80x9cself-aligned contactxe2x80x9d. In the prior art, a self-aligned contact is formed in the following manner. First, a gate electrode is covered with a silicon nitride film. Then, an interlevel dielectric film of silicon dioxide, for example, is etched using the silicon nitride film as an etch stopper so as to form a contact hole reaching a diffused layer. Thus, the gate electrode should preferably be completely covered with the silicon nitride film.
FIG. 8 illustrates a cross section of a prior art semiconductor device. As shown in FIG. 8, trench isolations 102 are formed on an Si substrate 101 and a transistor is formed in an active region surrounded by the trench isolations 102. The transistor includes: a gate insulating film 103 of silicon dioxide; a polysilicon gate electrode 104; an insulator cap 105 of silicon nitride; a pad oxide film 106 of silicon dioxide; and a nitride sidewall 107. As shown in FIG. 8, the gate electrode 104 is formed on the gate insulating film 103 and the insulator cap 105 is formed on the gate electrode 104. And the pad oxide film 106 covers the side faces of the gate electrode 104 and a part of the upper surface of the substrate 101. The nitride sidewall 107 covers the respective side faces of the gate electrode 104 and the insulator cap 105. The transistor further includes LDD regions 110 and heavily doped source/drain regions 111, both of which regions are defined within the Si substrate 101. And a contact 109 is provided to pass through an interlevel dielectric film 108 formed on the substrate 101 and to reach one of the heavily doped source/drain regions 111. Depending on the direction of a mask stacking error, the contact 109 comes into partial contact with the insulator cap 105 and the nitride sidewall 107 to serve as a self-aligned contact.
The semiconductor device may be fabricated in the following manner. First, silicon dioxide, polysilicon and silicon nitride films are deposited in this order on a semiconductor substrate 101 in which wells (not shown) are defined. Next, the silicon nitride and polysilicon films are patterned by photolithography and dry etching techniques, thereby forming the insulator cap 105 and gate electrode 104. In this process step, the silicon dioxide film is usually patterned into the same shape to form the gate insulating film 103. Then, heat treatment is conducted within oxygen ambient, thereby forming the pad oxide film 106 of silicon dioxide to cover the side faces of the gate electrode 104 and a part of the upper surface of the Si substrate 101. Thereafter, a silicon nitride film is deposited over the entire surface of the substrate and then etched back, thereby forming the sidewall 107 of silicon nitride over the respective side faces of the insulator cap 105 and the gate electrode 104. Subsequently, the interlevel dielectric film 108 is formed and the contact 109 is formed as an extension from the heavily doped source/drain regions 111.
In this structure, the polysilicon gate electrode 104 is covered with the silicon nitride insulator cap 105 and the nitride sidewall 107. Accordingly, if dry etching is performed using the silicon nitride film as an etch stopper to open the contact hole, then a self-aligned contact can be formed.
As can be seen, according to the conventional method for fabricating the semiconductor device, the pad oxide film 106 is formed as a thermal oxide film before the nitride sidewall 107 is formed. Without this pad oxide film 106, the nitride sidewall 107 would be in direct contact with the Si substrate 101. In such a situation, stress is applied through the nitride film to the gate insulating film 103, thus deteriorating the quality of the gate insulating film 103. In addition, since the transistors formed this way cannot recover from damage caused by a sintering process, the characteristics of resultant transistors are non-uniform. For these reasons, the pad oxide film 106 is required to prevent the nitride sidewall 107 from coming into direct contact with the Si substrate 101.
As semiconductor devices have been downsized and the number of those devices integrated has been increasing, it has become more and more necessary to reduce the resistance of the gate electrode thereof. For that purpose, a gate electrode for an MOS transistor with the single-layer polysilicon film shown in FIG. 8 is no longer preferred. Instead, a so-called xe2x80x9cpolycidexe2x80x9d or xe2x80x9cpoly-metalxe2x80x9d structure prevails these days. Specifically, in a recent gate electrode structure, a single-layer metal or metal compound (such as metal silicide or nitride) film or a multilayer structure thereof is deposited on a polysilicon film.
However, many of these metals or metal compounds like metal silicides or nitrides are poorly resistant to oxidation. Accordingly, the process step of forming the pad oxide film 106 such as that shown in FIG. 8 by thermal oxidation is not applicable to a semiconductor device including the polycide or poly-metal gate electrode.
An alternative method has also been proposed to prevent a silicon nitride film from coming into direct contact with a semiconductor substrate. According to the technique, a silicon dioxide film is deposited by a CVD process, for example, instead of forming a pad oxide film by thermal oxidation. FIG. 9 illustrates a cross section of a semiconductor device formed by such a method. As shown in FIG. 9, an upper gate electrode 104b made of a refractory metal (or a silicide thereof) is formed on a lower gate electrode 104a of polysilicon. A CVD pad oxide film 115 with an L cross section is formed to cover the respective side faces of the insulator cap 105 and the upper and lower gate electrodes 104b and 104a and part of the surface of the Si substrate 101. And the nitride sidewall 107 is formed on the CVD pad oxide film 115. The other members of the device are the same as those illustrated in FIG. 8.
In the structure shown in FIG. 9, however, when a contact hole is formed to pass through the interlevel dielectric film 108, an upper edge of the nitride sidewall 107 might be etched away unintentionally as in a region Ret shown in FIG. 9. The reason is believed to be as follows. According to this method, when the nitride sidewall 107 and the insulator cap 105 are exposed inside the contact hole, the upper edge of the CVD pad oxide film 115 is also exposed there. Thus, if the upper edge of the CVD pad oxide film 115 is etched, then the nitride sidewall 107 is etched from both sides, thus adversely decreasing the etch selectivity between the interlevel dielectric film of silicon dioxide and the silicon nitride film.
An object of the present invention is providing a highly reliable semiconductor device and a method for fabricating the same by protecting a gate electrode using a silicon nitride film even when the gate electrode has the poly-metal or polycide structure, in which a low-resistance layer poorly resistant to oxidation is formed on a polysilicon film.
A semiconductor device according to the present invention includes a gate insulating film formed on a semiconductor substrate and a gate electrode. The gate electrode is formed on the gate insulating film and includes lower and upper electrodes that are stacked in this order. The lower electrode is made of silicon, while at least an uppermost part of the upper electrode is made of a material containing a metal. The device further includes an insulator cap formed on the gate electrode. At least an uppermost part of the insulator cap is made of silicon nitride. The device further includes: a first nitride sidewall formed to cover at least respective side faces of the upper electrode of the gate electrode and the insulator cap; and a pad oxide film formed on part of the side faces of the gate electrode and part of the upper surface of the semiconductor substrate. That part of the side faces of the gate electrode is not covered with the first nitride sidewall. The device further includes: a second nitride sidewall formed on the first nitride sidewall and the pad oxide film; doped regions, which are defined within the semiconductor substrate and located beside the gate electrode; an interlevel dielectric film formed on the semiconductor substrate; and a contact, which passes through the interlevel dielectric film to reach one of the doped regions and is self-aligned with the gate electrode.
In this structure, the upper and side faces of the upper electrode of the gate electrode, which includes a part made of a material containing a metal poorly resistant to oxidation, are covered with the nitride films. Thus, when an oxidation process step is performed to form the pad oxide film, the upper electrode receives no damage. Also, even if the second nitride sidewall and the insulator cap are exposed within a contact hole when a contact is formed by filling in the contact hole, the etch selectivity of the second nitride sidewall does not decrease. This is because the first nitride sidewall is located under the upper edge portion of the second nitride sidewall. In addition, the pad oxide film is interposed between these nitride sidewalls and at least the lower edge portion of the lower electrode. Accordingly, no stress is applied from the nitride films to the lower electrode and to the semiconductor substrate. Thus, a semiconductor device including not only a low-resistance gate electrode but also a self-aligned contact can be obtained without risking the reliability thereof.
In one embodiment of the present invention, the upper and lower electrodes may be stacked one upon the other such that the upper electrode is in direct contact with the upper surface of the lower electrode. In such an embodiment, a resultant MISFET with a poly-metal or polycide gate structure can attain the above effects.
In this particular embodiment, the first nitride sidewall preferably covers part of the side faces of the lower electrode. The pad oxide film is preferably formed on the other part of the side faces of the lower electrode, except for that part covered with the first nitride sidewall, and on a part of the upper surface of the semiconductor substrate.
In another embodiment of the present invention, the semiconductor device may further include an interelectrode insulating film interposed between the upper and lower electrodes. The upper electrode may be a control gate electrode, while the lower electrode may be a floating gate electrode.
In such an embodiment, a semiconductor device, which includes not only a low-resistance gate electrode but also a self-aligned contact and functions as a memory cell transistor for a nonvolatile memory, can be obtained without risking the reliability thereof.
In this particular embodiment, the upper electrode may be formed out of a single layer metal film. Alternatively, the upper electrode may have a multilayer structure, in which a silicon film and a conductor film containing a metal are stacked in this order.
In another alternative embodiment, the first nitride sidewall may be formed on the side faces of the upper electrode and on at least part of the side faces of the interelectrode insulating film. The pad oxide film may be formed at least over the entire side faces of the lower electrode. In such an embodiment, the first nitride sidewall is formed on the side faces of the upper electrode over the interelectrode insulating film, while the pad oxide film is formed on the side faces of the lower electrode under the interelectrode insulating film.
As still another alternative, the first nitride sidewall may be formed on the side faces of the upper electrode and the interelectrode insulating film and on part of the side faces of the lower electrode. The pad oxide film may be formed on the other part of the side faces of the lower electrode, except for that part covered with the first nitride sidewall, and on the part of the upper surface of the semiconductor substrate. In such an embodiment, a bird""s-beak-free interelectrode insulating film can be obtained and high capacitance coupling is attainable between the control and floating gate electrodes.
An inventive method for fabricating a semiconductor device includes the step of a) forming a gate insulating film, a lower electrode film made of silicon, an upper electrode film and a cap insulating film in this order on a semiconductor substrate. At least an uppermost part of the upper electrode film is made of a material containing a metal. At least an uppermost part of the cap insulating film is made of silicon nitride. The method further includes the steps of: b) etching at least the cap insulating film and the upper electrode film to form an insulator cap and an upper electrode of a gate electrode and stopping etching no later than completion of etching the lower electrode film; c) forming a first nitride sidewall on respective side faces of the insulator cap and the upper electrode of the gate electrode that have been patterned in the step b) and on an etched part of the side faces of the lower electrode film; d) etching non-etched parts of the lower electrode film using the first nitride sidewall and the insulator cap as a mask, thereby forming a lower electrode for the gate electrode; e) forming a pad oxide film by thermal oxidation on part of the side faces of the lower electrode of the gate electrode that is located under the first nitride sidewall and on a part of the upper surface of the semiconductor substrate; f) forming a second nitride sidewall on the first nitride sidewall and on the pad oxide film; g) defining doped regions within the semiconductor substrate such that the doped regions are located beside the gate electrode; h) forming an interlevel dielectric film over the semiconductor substrate; and i) forming a contact hole that passes through the interlevel dielectric film to reach one of the doped regions and is self-aligned with the gate electrode.
According to this method, when the pad oxide film is formed in the step e), the side faces of the upper electrode, of which at least the uppermost part is made of a material containing a metal, have already been covered with the first nitride sidewall in the step d). Thus, that metal part of the upper electrode does not deteriorate due to oxidation. Also, even if the contact hole overlaps with the gate electrode when a contact is formed in the step i), the first and second nitride sidewalls and the insulator cap can prevent the contact hole from reaching the gate electrode. In addition, when the device is completed, the lower edge portion of the lower electrode is covered with the pad oxide film on its side faces. Thus, no stress is applied from the second nitride sidewall to the semiconductor substrate or the gate electrode. As a result, a semiconductor device with a highly reliable self-aligned contact structure can be formed.
In one embodiment of the present invention, the upper and lower electrode films may be stacked one upon the other in the step a) such that the upper electrode film is in direct contact with the upper surface of the lower electrode film. In such an embodiment, a transistor with a highly reliable self-aligned contact structure, which can function as a MISFET, can be formed.
In this particular embodiment, the etching step b) is preferably stopped after part of the lower electrode film has been etched and the other part thereof has not been etched yet. In the step c), the first nitride sidewall is preferably formed on the etched part of the side faces of the lower electrode film. And in the step e), the pad oxide film is preferably formed on the other part of the side faces of the lower electrode and on the part of the upper surface of the semiconductor substrate. In such an embodiment, the side faces of the upper electrode film can be entirely covered with the first nitride sidewall.
Alternatively, in the step a), the lower electrode film of silicon may be made up of upper and lower silicon film portions that can be etched selectively with respect to each other. In the step c), the lower silicon film portion may be used as an etch stopper. In such an embodiment, the etching step b) can be stopped at an easily controllable timing.
In another embodiment of the present invention, an interelectrode insulating film may be formed in the step a) between the upper and lower electrode films. In the step b), a control gate electrode may be formed as the upper electrode. And in the step d), a floating gate electrode may be formed as the lower electrode. In such an embodiment, a semiconductor device with a highly reliable self-aligned contact structure, which functions as a memory cell transistor for a nonvolatile memory, can be obtained.
In this particular embodiment, a single layer metal film may be formed in the step a) as the upper electrode film. Alternatively, a silicon film and a conductor film containing a metal may be stacked in the step a) in this order to form the upper electrode film.
As another alternative, the interelectrode insulating film may be used in the step b) as an etch stopper and etching may be stopped when the lower electrode film is not etched at all. In the step c), the first nitride sidewall may be formed on the side faces of the upper electrode and on at least part of the side faces of the interelectrode insulating film. And in the step e), the pad oxide film may be formed at least over the entire side faces of the lower electrode. In such an embodiment, the etching step b) can be stopped at an easily controllable timing.
As still another alternative, the etching step b) may be stopped after part of the lower electrode film has been etched but the other part thereof has not been etched yet. In the step c), the first nitride sidewall may be formed on the side faces of the upper electrode and the interelectrode insulating film and on part of the side faces of the lower electrode film. And in the step e), the pad oxide film may be formed on the other part of the side faces of the lower electrode, except for the part covered with the first nitride sidewall, and on the part of the upper surface of the semiconductor substrate. In such an embodiment, when the pad oxide film is formed, the side faces of the interelectrode insulating film have already been covered with the first nitride sidewall, thus preventing any bird""s beak from being formed at the edges of the interelectrode insulating film. As a result, high capacitance coupling is attainable between the control and floating gate electrodes in the semiconductor device.